1. Field of the Invention
The present invention relates to a carry lookahead circuit for a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 presents a block diagram of a conventional carry lookahead circuit for a semiconductor integrated circuit. An operation circuit 100 comprises five arithmetic units BLK0 to BLK4 connected in parallel. The processing speed of a carry lookahead circuit is restricted by the propagation time of a carry signal, which is generated as the result of an operation, from the lowest digit of each arithmetic unit to the highest digit. As the number of digits increases, the scale of the logic circuits that constitute the carry lookahead circuit becomes larger. To cope with this problem, individual arithmetic units each have a 4-bit structure and are cascade-connected to ensure an arbitrary number of bits. For instance, a binary-operation circuit having 20-bit input data A0 to A19 and B0 to B19 comprises an operation circuit 100 for performing an operation and a carry lookahead circuit 101 which looks ahead a carry signal that is input every four bits.
As mentioned above, the operation circuit 100 includes the arithmetic unit BLK0, arithmetic unit BLK1, arithmetic unit BLK2, arithmetic unit BLK3 and arithmetic unit BLK4. The arithmetic unit BLK0 has eight data input terminals A0 to A3 and B0 to B3 to receive two pieces of 4-bit data, a carry input terminal CI.sub.0, a carry output terminal CO.sub.0 and a carry condition output terminal D.sub.0. Likewise, the arithmetic unit BLK1 has eight data input terminals A4-A7 and B4-B7, a carry input terminal CI.sub.1, a carry output terminal CO.sub.1 and a carry condition output terminal D.sub.1. The arithmetic unit BLK2 has eight data input terminals A8-A11 and B8-B11, a carry input terminal CI.sub.2, a carry output terminal CO.sub.2 and a carry condition output terminal D.sub.2. The arithmetic unit BLK3 has eight data input terminals A12-A15 and B12-B15, a carry input terminal CI.sub.3, a carry output terminal CO.sub.3 and a carry condition output terminal D.sub.3 . The arithmetic unit BLK4 has eight data input terminals A16-A19 and B16-B19, a carry input terminal CI.sub.4, a carry output terminal CO.sub.4 (CYO) and a carry condition output terminal D.sub.4.
The carry lookahead circuit 101 has its 0-th bit input carry signal line connected to the carry input terminal CI.sub.0 of the arithmetic unit BLK0. The carry condition output terminal D.sub.0 of the arithmetic unit BLK0 and the 0-th bit input carry signal line are connected to two input terminals of an AND gate 1. The carry output terminal CO.sub.0 of the arithmetic unit BLK0 and the output terminal of the AND gate 1 are connected to two input terminals of an OR gate 2. The output terminal of the OR gate 2 is connected to the carry input terminal CI.sub.1 of the arithmetic unit BLK1.
The carry condition output terminal D.sub.1 of the arithmetic unit BLK1 and the carry output terminal CO.sub.0 of the arithmetic unit BLK0 are connected to two input terminals of an AND gate 3. The carry condition output terminal D.sub.1 of the arithmetic unit BLK1, the carry condition output terminal D.sub.0 of the arithmetic unit BLK0 and the 0-th bit input carry signal line are connected to three input terminals of an AND gate 4. The carry output terminal CO.sub.1 of the arithmetic unit BLK1, and the output terminals of the AND gates 3 and 4 are connected to three input terminals of an OR gate 5. The output terminal of the OR gate 5 is connected to the carry input terminal CI.sub.2 of the arithmetic unit BLK2.
The carry condition output terminal D.sub.2 of the arithmetic unit BLK2 and the carry output terminal CO.sub.1 of the arithmetic unit BLK1 are connected to two input terminals of an AND gate 6. The carry condition output terminal D.sub.2 of the arithmetic unit BLK2, the carry condition output terminal D.sub.1 of the arithmetic unit BLK1 and the carry output terminal CO.sub.0 of the arithmetic unit BLK0 are connected to three input terminals of an AND gate 13. The carry condition output terminal D.sub.2 of the arithmetic unit BLK2, the carry condition output terminal D.sub.1 of the arithmetic unit BLK1, the carry condition output terminal D.sub.0 of the arithmetic unit BLK0 and the 0-th bit input carry signal line are connected to four input terminals of an AND gate 14. The carry output terminal CO.sub.2 of the arithmetic unit BLK2 and the output terminals of the AND gates 6, 13 and 14 are connected to four input terminals of an OR gate 15. The output terminal of the OR gate 15 is connected to the carry input terminal CI.sub.3 of the arithmetic unit BLK3.
The carry condition output terminal D.sub.3 of the arithmetic unit BLK3 and the carry output terminal CO.sub.2 of the arithmetic unit BLK2 are connected to two input terminals of an AND gate 8. The carry condition output terminal D.sub.3 of the arithmetic unit BLK3, the carry condition output terminal D.sub.2 of the arithmetic unit BLK2, and the carry output terminal CO.sub.1 of the arithmetic unit BLK1 are connected to three input terminals of an AND gate 9. The carry condition output terminal D.sub.3 of the arithmetic unit BLK3, the carry condition output terminal D.sub.2 of the arithmetic unit BLK2, the carry condition output terminal D.sub.1 of the arithmetic unit BLK1 and the carry output terminal CO.sub.0 of the arithmetic unit BLK0 are connected to four input terminals of an AND gate 10. The carry condition output terminal D.sub.3 of the arithmetic unit BLK3, the carry condition output terminal D.sub.2 of the arithmetic unit BLK2, the carry condition output terminal D.sub.1 of the arithmetic unit BLK1, the carry condition output terminal D.sub.0 of the arithmetic unit BLK0 and the 0-th bit input carry signal line are connected to five input terminals of an AND gate 11. The carry output terminal CO.sub.3 of the arithmetic unit BLK3, and the output terminals of the AND gates 8, 9, 10 and 11 are connected to five input terminals of an OR gate 12. The output terminal of the OR gate 12 is connected to the carry input terminal CI.sub.4 of the arithmetic unit BLK4.
FIG. 2 presents a block diagram of arithmetic and logic units which constitute each of the arithmetic units BLK0-BLK4. The arithmetic units BLK1-BLK4 in the operation circuit 100 each comprise arithmetic and logic units (ALUs) 21, 22, 23 and 24 which are so connected that each carry input terminal Ci receives a signal from the carry output terminal Co of the preceding stage. The ALUs 21 to 24 have data input terminals A and B to which 4-bit data An to A(n+3) (n=0, 4, 8, 12, 16) and 4-bit data Bn to B(n+3) are input. The lookahead carry signal up to the preceding arithmetic unit is input to the first ALU 21. Each of the terminals SUMs which output signals produced as the result of the operation is connected to input terminal of an AND gate 25. The output terminal D of the AND gate 25 serves as the carry condition output terminal D.sub.0, D.sub.1, D.sub.2, D.sub.3 or D.sub.4 to transfer the carry signal of up to the preceding arithmetic unit forward.
The operation of the prior art circuit shown in FIG. 1 will now be described referring to FIGS. 1 and 2. The carry input terminal CI.sub.0 of the arithmetic unit BLK0 receives a carry C that is input at the 0-th bit. The carry signal from the preceding stage which is to be input to the carry input terminal CI.sub.1 of the arithmetic unit BLK1 is looked ahead by the output of the OR gate 2 or the logical sum of the output of the AND gate 1, which is the logical product of the carry C input at the 0-th bit and the carry condition D.sub.0 of the arithmetic unit BLK0, and the carry output CO.sub.0 generated in the arithmetic unit BLK0.
The lookahead carry signal from the preceding stage which is to be input to the arithmetic unit BLK2 is looked ahead by the output of the OR gate 5 or the logical sum of the output of the AND gate 4, which is the logical product of the carry C input at the 0-th bit and the carry conditions D.sub.0 and D.sub.1 of the arithmetic units BLK0 and BLK1 respectively, the output of the AND gate 3, which is the logical product of the carry output CO.sub.0 generated in the arithmetic unit BLK0 and the carry condition D.sub.1 of the arithmetic unit BLK1, and the carry output CO.sub.1 generated in the arithmetic unit BLK1.
The lookahead carry signal from the preceding stage which is to be input to the arithmetic unit BLK3 is looked ahead by the output of the OR gate 15 or the logical sum of the output of the AND gate 14, which is the logical product of the carry C input at the 0-th bit and the carry conditions D.sub.0, D.sub.1 and D.sub.2 of the arithmetic units BLK0, BLK1 and BLK2 respectively, the output of the AND gate 13, which is the logical product of the carry output CO.sub.0 generated in the arithmetic unit BLK0 and the carry conditions D.sub.1 and D.sub.2 of the arithmetic units BLK1 and BLK2 respectively, the output of the AND gate 6, which is the logical product of the carry output CO.sub.1 generated in the arithmetic unit BLK1 and the carry condition D.sub.2 of the arithmetic unit BLK2, and the carry output CO.sub.1 generated in the arithmetic unit BLK2.
The lookahead carry signal from the preceding stage which is to be input to the arithmetic unit BLK4 is looked ahead by the output of the OR gate 12 or the logical sum of the output of the AND gate 11, which is the logical product of the carry C input at the 0-th bit and the carry conditions D.sub.0, D.sub.1, D.sub.2 and D.sub.3 of the arithmetic units BLK0, BLK1, BLK2 and BLK3 respectively, the output of the AND gate 10, which is the logical product of the carry output CO.sub.0 generated in the arithmetic unit BLK0 and the carry conditions D.sub.1, D.sub.2 and D.sub.3 of the arithmetic units BLK1, BLK2 and BLK3 respectively, the output of the AND gate 9, which is the logical product of the carry output CO.sub.1 generated in the arithmetic unit BLK1 and the carry conditions D.sub.2 and D.sub.3 of the arithmetic units BLK2 and BLK3 respectively, the output of the AND gate 8, which is the logical product of the carry CO.sub.2 generated in the arithmetic unit BLK2 and the carry condition D.sub.3 of the arithmetic unit BLK3, and the carry output CO.sub.3 of the arithmetic unit BLK3.
It is apparent from the above that in the conventional carry lookahead circuit in a (4.times.n)-bit operation circuit, the lookahead carry signal from the preceding stage which is to be input to the m-th arithmetic unit BLK(m-1) is acquired by obtaining
the logical product of the carry C input at the 0-th bit and the carry conditions D.sub.0 -D.sub.m-2 from the first arithmetic unit BLK0 to the (m-1)-th arithmetic unit BLK(m-2) respectively, and
for each carry output CO.sub.p (0.ltoreq.p.ltoreq.m-3) of the first to (m-2)-th carry outputs CO.sub.0 -CO.sub.m-3, the logical product of the associated carry signal CO.sub.p and the carry conditions D.sub.p+1 -D.sub.m-2 of the next ((p+1)-th) arithmetic unit BLK(p+1) to the (m-1)-th arithmetic unit BLK(m-2) respectively,
and then obtaining the logical sum of the individual logical products, obtained for the carry C and the respective carry outputs CO.sub.0 -CO.sub.m-3, and the (m-1)-th carry output CO.sub.m-2.
In other words, the lookahead carry signal can be expressed by ##EQU1##
In the conventional carry lookahead circuit in a (4.times.n)-bit semiconductor integrated circuit, the circuitry up to immediately before the m-th arithmetic unit BLK(m-1) or up to the (m-1)-th arithmetic unit BLK(m-2) includes 2.times.m AND gates and (m-1) OR gates. In addition, the AND gates 13 and 14, which are not essential in executing the carry lookahead operation, are provided to improve the operation speed of the entire carry lookahead circuit. This design undesirably increases the area the elements constituting the carry lookahead circuit occupy on the chip of the semiconductor integrated circuit. Further, the number of fan-outs of the inputs of the 2.times.m AND gates, namely, the carry C input at the 0-th bit, the carry outputs produced from the individual arithmetic units BLK and the carry conditions, increases to increase the load capacity of each logic gate.